1. Field of Invention
The present invention relates to a level shifter that has a simple configuration and that quickly converts a low-amplitude logic signal into a high-amplitude logic signal. The present invention also relates to an electro-optical apparatus incorporating the level shifter.
2. Description of Related Art
In recent years, electro-optical apparatuses that allow display by electro-optical change in electro-optical materials, such as liquid crystal and organic EL (electroluminescence) materials, have become widely used in various information processing apparatuses and television sets as alternative display devices to cathode-ray tube (CRT) displays.
Such electro-optical apparatuses can be broadly classified, by their driving methods, into active matrix type apparatuses, in which pixels are driven by non-linear devices, such as transistors and diodes, and passive matrix type apparatuses, in which pixels are driven without using non-linear devices. It is believed that electro-optical apparatuses of the former type, i.e., active matrix type apparatuses, provide higher quality display because pixels are driven independently of each other therein.
An electro-optical apparatus of the active matrix type is constructed as follows. In an electro-optical apparatus of the active matrix type, pixel electrodes are formed respectively in association with intersections of scanning lines extending in a row direction and data lines extending in a column direction. Furthermore, non-linear devices, such as thin-film transistors, that turn on and off according to scanning signals supplied to the scanning lines, are disposed between the pixel electrodes and the data lines at the intersections, and an opposing electrode is formed so as to oppose the pixel electrodes via an electro-optical material.
A relatively high voltage is required in order to drive the electro-optical material and the non-linear devices. On the other hand, an external control circuit for supplying a clock signal, a control signal, etc., for driving to the electro-optical apparatus is usually implemented by CMOS circuits, and the amplitude of a logic signal therefor is on the order of 3 to 5 V. Thus, the electro-optical apparatus typically includes an amplitude conversion circuit (hereinafter xe2x80x9clevel shifterxe2x80x9d) for converting a low-amplitude logic signal into a high-amplitude logic signal at an output of a driving circuit for driving the scanning lines and the data lines or at an input of a clock signal, etc.
In recent years, a strong demand has arisen for higher resolution and a larger number of steps in intensity level of display in electro-optical apparatuses. Thus, in electro-optical apparatuses, fast operation of level shifters as well as fast operation of driving circuits themselves is required. Furthermore, in addition to higher resolution, a larger number of pixels per unit length is demanded, requiring a reduction in scale of circuitry.
The present invention addresses the situation described above, and provides a level shifter that has a simple configuration with reduced scale of circuitry and that allows fast operation. The present invention also provides an electro-optical apparatus incorporating such a level shifter.
In order to address the above situation, a level shifter according to the present invention includes a first capacitor, to a first end of which a low-amplitude logic signal is input; a first offset circuit to apply a first offset voltage to a second end of the first capacitor; a second capacitor, to a first end of which the low-amplitude logic signal is input; a second offset circuit to apply a second offset voltage to a second end of the second capacitor; and first and second switching elements, connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor. The first switching element is connected to the second end of the first capacitor, while the second switching element is connected to the second end of the second capacitor in accordance with the offset voltages.
According to the above arrangement, a DC component is removed from the low-amplitude logic signal by each of the first and second capacitors, and the first and second offset voltages are applied by the first and second offset circuits, respectively. For example, the arrangement is such that the first switching element turns on if a signal voltage at the second end of the first capacitor is not higher than a first threshold value, which is set to be lower than the first offset voltage, and the second switching element turns on if a signal voltage at the second end of the second capacitor is at or above a second threshold value, which is set to be higher than the second offset voltage, so that the first and the second switching elements, the operating points thereof having been modified, complementarily turn on and off.
In a preferred mode, as in the above example, the first switching element turns on if a signal voltage at the second end of the first capacitor is not higher than a first threshold value, which is set to be lower than the first offset voltage, and the second switching element turns on if a signal voltage at the second end of the second capacitor is at or above a second threshold value, which is set to be higher than the second offset voltage.
In the above arrangement, preferably, the first switching element is a P-channel transistor and the second switching element is an N-channel transistor, the first offset circuit is implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the supply line of the reference voltage, a voltage at a node therebetween serving as the first offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor, and the second offset circuit is implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the supply line of the reference voltage, a voltage at a node therebetween serving as the second offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor.
According to the above arrangement, even if transistor characteristics of one channel type differ from those of the other channel type, the first or the second offset voltage changes so as to offset the difference.
The above arrangement is suitable for a low-amplitude logic signal that has a frequency that is sufficiently high in relation to the capacitance of the first and the second capacitors and that changes regularly (e.g., a clock signal having a duty ratio of 50%).
However, a problem exists that when a logic signal having a low frequency is input, or when an input logic signal is maintained at the same logic level, on/off status of the first and the second switching elements becomes indeterminate.
Thus, preferably, in the above arrangement, the offset voltages of the first and the second offset circuits are changed according to the output of the level shifter, that is, according to the voltage at the node between the first and the second switching elements.
According to the above arrangement, once on/off status of the first and the second switching elements is determined, the potential at the output terminal is subsequently prevented from becoming indeterminate, due to voltage attenuation of the first or the second capacitor at the output terminal.
However, in an initial state, for example, immediately after power-up, the potential at the output terminal inevitably becomes indeterminate unless the logic level of the input logic signal transits. Accordingly, in a preferred arrangement, an initialization circuit to apply an initialization voltage to the second end of the first capacitor and to the second end of the second capacitor is provided so that the first and the second switching elements turn on and off exclusively with each other regardless of the output of the level shifter.
In particular, in the first and second offset circuit, a problem exists that generally a small current flows to cause a waste of power. For example, if the first and second offset circuits are implemented by N-channel transistors and P-channel transistors as described above, a small current flows therebetween, causing a waste of power.
Accordingly, in this arrangement, preferably, the xe2x80x9cpower supply voltagesxe2x80x9d and the xe2x80x9creference voltagesxe2x80x9d supplied to the offset circuits are at least partially replaced with the xe2x80x9clow-amplitude logic signal.xe2x80x9d According to this arrangement, for example, if the offset circuits are implemented by N-channel transistors and P-channel transistors as described above, the potential difference therebetween changes in synchronization with the low-amplitude logic signal. Thus, periods of reduced potential difference, compared with the arrangement in which the power supply voltages and the reference voltages are supplied, can be achieved. The reduction in the potential difference serves to reduce power consumption.
Although the low-amplitude logic signal is used to reduce the potential difference between the N-channel transistors and the P-channel transistors constituting the offset circuits in the above arrangement, the present invention is not limited thereto, and a signal synchronized with the low-amplitude logic signal may be used.
Which of the power supplies supplied to the offset circuits is replaced with the low-amplitude logic signal or the signal synchronized with the low-amplitude logic signal is a matter of design determined in accordance with the operation mode of level shifter.
As an arrangement to avoid a waste of power, a level shifter may include a second capacitor, to a first end of which a low-amplitude logic signal is input; a second offset circuit to apply a second offset voltage to a second end of the second capacitor; and first and second switching elements, connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal. The first switching element turns on when the low-amplitude logic signal is L level, and the second switching element turns on when a signal voltage at the second end of the second capacitor is at or above a second threshold voltage, which is set to be higher than the second offset voltage.
According to the above arrangement, essentially, the first capacitor and the first offset circuit are absent in the level shifter according to the present invention described above, so that the low-amplitude logic signal is directly input to the first switching element, the first switching element turning on when the logic signal is at L level. Accordingly, since the first offset circuit itself is absent, power consumption therein need not be considered.
Since the first capacitor and the first offset circuit are absent as described above, the constituent devices are eliminated, serving to enhance manufacturing yield and to reduce cost.
As an alternative arrangement, a level shifter may include a first capacitor, to a first end of which a low-amplitude logic signal is input; an offset circuit to apply a first offset voltage to a second end of the first capacitor; and first and second switching elements, connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal. The first switching element turns on if a signal voltage at the second end of the first capacitor is at or below a first threshold voltage, which is set to be lower than the first offset voltage, and the second switching element turns on when the low-amplitude logic signal is at H level. The choice between the arrangements is a matter of design determined in accordance with the operation mode of level shifter.
By applying a level shifter according to the present invention to a driving circuit of an electro-optical apparatus, resolution and number of steps in intensity level can be considerably increased. Furthermore, scale of circuitry can be reduced.
As described hereinabove, according to the present invention, a level shifter that has a simple configuration and that allows fast operation can be implemented.
The above and other advantages of the present invention will become more apparent from the following description of embodiments.